Karthik Wali: Two Decades Beneath The Software

That view comes from a career spent in register-transfer level (RTL) design, the craft of describing a chip’s behavior in code that eventually becomes gates. Wali has worked with RISC-V, ARM, MIPS and ARC processors, integrated CPU and peripheral IP into systems-on-chip over AXI, AHB and APB buses, and carried designs through synthesis, power analysis, test planning and debug.

Learning the craft in Bangalore

Wali’s career started the month after his degree did. He graduated in June 2006 with a bachelor’s in electronics and communication from SDM College of Engineering and Technology, and in July joined KarMic Design Centre in Bangalore as a member of technical staff.

KarMic did design work for outside clients, which put a young engineer in front of very different problems. For Texas Instruments he worked on power-management IC verification and an SPI interface. For Saankhya Labs he helped design VLIW processors for a digital-TV modulator chip.

That second project took him inside the CPU. He micro-architected register files, instruction decoders, load-store units and a JTAG debug unit: the parts that decide how a processor reads its instructions and moves its data, and how engineers see inside it when something fails.

In December 2011, after five years at KarMic, he moved to Microchip Technology in Bangalore as a senior design engineer on 32-bit microcontrollers and microprocessors. There he integrated the MIPS microAptiv core, built memory wrappers and wrote system-level SystemVerilog. Fitting a licensed processor core into a complete chip became a thread that runs through the rest of his career.

Chicago, then San Jose

Wali’s next step was academic. In May 2014 he completed a master’s in electrical engineering at the Illinois Institute of Technology in Chicago.

By December he was in Silicon Valley, joining LG Electronics Mobile Research USA in San Jose as a senior design engineer. He stayed nearly six years, the longest stretch of his career and the one with the widest scope.

Building from scratch at LG

At LG, Wali worked across a Scalable Computing Core IP, a System Level Cache and an Always on Platform, an IoT chip built around two ARC cores. The work ran from single blocks up to whole systems.

He designed a four-stage, high-speed RISC-V core to the RV32IM specification, configurable for memory size, data width and pipeline options. He also implemented a Softmax accelerator, the function at the end of many neural networks that turns raw scores into probabilities, in both IEEE 754 single-precision floating point and fixed point. Building it both ways meant weighing the same math against different costs in area, power and accuracy.

On the System Level Cache he went after power. He added dynamic clock gating, way-based shutdown and a light-sleep mode, so that parts of the cache stop drawing power when they are not needed.

For the Always on Platform he owned SoC integration, produced FPGA bitfiles for Kintex boards, and led a team of verification engineers in setting up the chip’s verification flow and test cases. The role had him managing engineers as well as writing the design.

Safety features and neural-network silicon

In September 2020 Wali joined Synopsys in Mountain View as an ASIC staff design engineer on its ARC EM processor cores. He added new security and safety features, made RTL changes and built feature sets that customers had asked for. The stint lasted about eight months, but it put him on the other side of a processor family he had built a platform around at LG.

In June 2021 he moved to Amazon Lab126 in Mountain View, where his work centers on neural-network IP. He has designed a RISC-V co-processor interface, the datapath for a depthwise convolution (DW CONV2D) instruction, a floating-point datapath and an IOMMU unit, and he works on timing optimization.

The IOMMU is the hardware that governs which memory a device is allowed to reach. It is the kind of isolation Wali argues safety-critical systems depend on, built directly into the silicon.

How he thinks

Twenty years at this layer have left Wali with firm views about where hardware projects go wrong.

The first is that the industry often judges AI hardware by the wrong numbers. Spec sheets lead with peak compute, but in his experience the cost of moving data into and out of an accelerator, and of integrating it with the rest of the chip, often decides real-world performance. “It is a trap many teams walk into because peak throughput is easy to measure and interface cost is not,” he says.

The second is that the hardest properties, including isolation between workloads, numerical precision and resilience to subtle faults, belong in the architecture rather than in later patches. He points to timing-related defects that slip past verification and surface in finished silicon as intermittent, hard-to-diagnose faults. “Those bugs are methodology failures, not coding failures,” he says.

He expects open instruction sets such as RISC-V to play a growing role, giving designers a standard way to add specialized capabilities without reinventing the surrounding system. It is a view grounded in his own work: a RISC-V core at LG, and a RISC-V co-processor interface at Lab126.

The third concerns AI in his own field. Wali has worked with AI-driven automation in the chip design flow and expects agentic tools to tie specification, design and verification more closely together. He is clear that design intent and verification ownership stay with the engineer. “A common misconception is that AI tooling replaces that judgment,” he says. “In practice it raises the premium on it.”

At a glance

• Based in: San Jose, California

• Education: MS, Electrical Engineering, Illinois Institute of Technology (2014); BE, Electronics and Communication, SDM College of Engineering and Technology (2006)

• Processor architectures: RISC-V, ARM, MIPS, ARC

• Design languages: Verilog, VHDL, SystemVerilog